1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and more specifically, to a delta-sigma analog-to-digital converter that partially powers-down between conversion cycles for lower sample rates.
2. Background of the Invention
Delta-sigma modulators are in widespread use in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), in which they provide very linear behavior and simple implementation due to the reduced number of bits used in the analog signal comparison. Delta-sigma modulators can be implemented with a high level of control of the frequency distribution of “quantization noise”, which is the difference between the ideal output value of the modulator as determined by the input signal and the actual output of the modulator provided by a quantizer. The relative simplicity of the architecture and the ability to finely control the quantization noise makes delta-sigma converter implementations very desirable.
The delta-sigma modulator based ADC typically includes an analog loop filter that receives an input signal and a quantizer that converts the analog output of the loop filter to a digital representation. A feedback signal provided from the output of the quantizer is introduced to the analog loop filter to close the loop such that the average output of the quantizer is equal to the value of the input signal. The output of the quantizer is then filtered by a low-pass digital filter having a large number of taps, in order to provide an accurate conversion result from the quantizer output, which typically includes hundreds of values per conversion cycle.
Since the operation of the delta-sigma modulator based ADC as described above is a quasi-continuous process within both the loop filter and the digital low-pass filter at the output, delta-sigma modulator based ADCs are typically designed for a fixed sample rate, or a sample rate that is selectable over a small range. The ADCs are typically operated continuously, unlike so-called “flash” ADCs or successive-approximation ADCs, which can be used to acquire a single sample and then be shut down between sampling/conversion cycles in order to save power at lower sampling rates. Interrupting the operation of the converter in order to save power between samples will cause disruption of the operation of the analog loop filter.
When multiple sample rates are supported by a delta-sigma ADC, the digital low-pass filter that renders the converter output is typically scaled by changing its clock frequency and the clock rate of the modulator is also changed. Therefore, in order to support widely varying sample rates in an ADC integrated circuit using a delta-sigma modulator, the power required for operating analog portion of the converter will be that required to support the higher clock rate in the modulator. Also, the digital low-pass filter that provides the output of the converter is also typically changed when a different sample rate is selected, so that the proper stop-band performance is attained at the lower sampling rate.
Therefore, it would be desirable to provide a delta-sigma ADC that can be placed at least partly in a power-saving mode between conversions when a lower sample rate is selected.